With scaling both in memory and complementary metal oxide (CMOS) logic fabrication, a method for achieving void free and pinhole free fillings of narrow cavities, trenches, gaps, etc. which may have high aspect ratios, may be desired. For example, void free and pinhole free fillings of shallow trench isolation structures, that have lateral dimensions below 40 nm, with an adequate dielectric, may be used in some integrated circuits.
Thus, there is a need for a method for forming fillings in integrated circuits.